IEEE

1364-2005 - IEEE Standard for Verilog Hardware Description Language

Abstract: The Verilog hardware description language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it ...
GitHub

SED: A Simple Encoder-Decoder for Open-Vocabulary Semantic Segmentation

We propose an encoder-decoder for open-vocabulary semantic segmentation comprising a hierarchical encoder-based cost map generation and a gradual fusion decoder. We introduce a category early ...
IEEE

1364-2001 - IEEE Standard Verilog Hardware Description Language

Abstract: Supersedes 1364-1995. The Verilog(R) Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of ...
GitHub

Scalable Video Technology for HEVC Encoder (SVT-HEVC Encoder)

This project will no longer be maintained by Intel. Intel has ceased development and contributions including, but not limited to, maintenance, bug fixes, new releases, or updates, to this project.