EDN

How to achieve 1 trillion floating-point operations-per-second in an FPGA

Based on recent technological developments, high-performance floating-point signal processing can, for the very first time, be easily achieved using FPGAs. To date, virtually all FPGA-based signal ...
EDN

How to implement double-precision floating-point on FPGAs

Floating-point arithmetic is used extensively in many applications across multiple market segments. These applications often require a large number of calculations and are prevalent in financial ...
Design-Reuse

Altera Introduces Industry's First FPGA Floating-Point FFT IP Cores

New Cores Leverage Stratix Device Family's Embedded DSP Blocks to Deliver a Cost-Effective Floating-Point FFT FPGA Solution San Jose, Calif., June 3, 2003—Altera Corporation (NASDAQ: ALTR) today ...
Electronic Design

VLIW DSP Engine Delivers 1 GFLOPS

The complex computational block on Atmel’s mAgic DSP core consists of four integer/floating-point multipliers, an adder, a subtractor, and two add-subtract integer ...
Semiconductor Engineering

Achieving Numerical Precision And Design Customization With Flexible Floating-Point IP

As defined by the IEEE 754 standard, floating-point values are represented in three fields: a significand or mantissa, a sign bit for the significand and an exponent field. The exponent is a biased ...
Design-Reuse

Using FPGAs to Improve the Performance of Radar, Navigation and Guidance Systems

Radar, navigation and guidance systems process data that is acquired using arrays of sensors. The energy delta from sensor to sensor over time holds the key to information such as targets, position or ...