TOKYO — Toshiba Corp. has developed a one-transistor, no-capacitor cell structure that it claims solves the difficulties encountered in producing DRAMs in sub-0.1-micron process technology. The ...

Tokyo – Renesas Technology Corp. has developed a new SRAM memory cell structure that combines SRAM and DRAM technologies. The device is about half the size of a conventional SRAM cell, but still has ...

NEO Semiconductor is once again announcing a new technology that hopes to revolutionize the state of DRAM memory. Today, the company unveiled two new 3D X-DRAM cell designs, 1T1C and 3T0C. The ...

On June 4, 1968, Robert Dennard was granted a patent for a single transistor, single capacitor DRAM cell design idea. This doesn’t sound earth-shattering today, but back in the sixties, this was a ...

Implemented in a standard 90-nm SOI process, the memory cell can be as small as 0.1 µm 2. That's about one-tenth the size of the smallest SRAM cells and less than half the size of most DRAM cells.

At the recent IEEE International Electron Devices Meeting (IEDM) in Washington, D.C., chipmakers presented papers on several technologies, including one unlikely topic—DRAM scaling. For years, it was ...

This week, at the 2020 International Electron Devices Meeting, imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, presents a novel dynamic random-access ...

SEOUL, South Korea--(BUSINESS WIRE)--Samsung Electronics Co., Ltd., the world leader in advanced memory technology, announced today that it has begun mass producing the industry’s first 10-nanometer ...

Apple, Samsung and others are developing the next wave of smartphones and tablets. OEMs want to integrate new memory schemes that provide more bandwidth at lower power. But there are some challenges ...

What just happened? A Californian company is launching what it calls a ground-breaking solution for increasing DRAM chip density with 3D stacking technology. The new memory chips will greatly improve ...