EDN

Cache Coherency Protocol Design

• Designed MSI, MESI and MOESI Coherence Protocols for a multiprocessor system. • Analyzed the Cache Performance for different cache configurations and different number of processors. • Modified the ...
Electronic Design

Formal Methodology Validates Cache-Coherence Protocol

Bugs in RTL code are problematic, but a bug in an architectural specification can be catastrophic. If the bug remains undetected until post-silicon debugging, the design process essentially starts all ...
Semiconductor Engineering

Heterogeneous Cache Coherence Requires A Common Internal Protocol

Machine learning and artificial intelligence systems are driving the need for systems-on-chip containing tens or even hundreds of heterogeneous processing cores. As these systems expand in size and ...
Design-Reuse

Synopsys Enables Next-Level of Productivity with Addition of System-Level Capabilities to Verification IP for Arm Cache Coherent Protocols

Synopsys, Inc. (NASDAQ: SNPS) announces the availability of advanced system-level capabilities in its next-generation VC Verification IP (VIP) for the Arm AMBA 4 ACE and AMBA 5 CHI protocols, as well ...
Design-Reuse

Using Cache Coherency to Verify the AMBA4 Protocol

The Jasper User Group Meeting was held on November 8 & 9 and was full of presentations on the diverse ways that users are applying formal techniques – some in areas where never before thought possible ...
Semiconductor Engineering

Toward Better Accelerators

In the not-too-distant past, the standard mobile application processor architecture was the predominant one used for most System-on-Chip (SoC) designs, but that is rapidly changing as new systems and ...
Computerworld

Web Caching Resources

Here’s a list of Web sites, white papers and books with more information about Web caching. Brian D. Davison’s Web Caching and Content Delivery Resources. This site is a great place to start. It has ...